Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into, or read from, the SRAM cell.
With the increasing down-scaling of integrated circuits, the operation voltages of integrated circuits are reduced, along with the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which measure how reliably the bits of the SRAM cells can be read from and written into, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.
FIG. 1 illustrates a portion of a conventional SRAM array, which includes a plurality of SRAM cells: C(1) through C(n) in a same column. SRAM cell C(1) is close to a pair of write drivers, which charge differential bit-lines BL and BL_. SRAM cell C(n) is close to the terminating end of the differential bit-lines BL and BL_, at which the differential bit-lines BL and BL_ terminate. Bit-lines BL and BL_ may be quite long, depending on the number of rows in the SRAM array. In very small-scale integrated circuits, the differential bit-lines BL and BL_ are very thin and narrow, and hence their resistances are no longer negligible. Since the voltages on bit-lines BL and BL_ are provided by the write drivers, the differential bit-line voltages at the terminating end of the differential bit-lines BL and BL_ will be noticeably lower than the voltages provided by the write drivers.
The reduced voltages on differential bit-lines BL and BL_result in the already low write margin to be further reduced. This may reduce the speed of write operations, and may even cause the failure of the write operations when the write margin reduces to 0 mV. This prevents the further desirable reduction of Vccmin, which is the higher one of the minimum voltages required to read data from, and write data into, SRAM memory cells. Therefore, new SRAM arrays having improved write margins are needed.